1. Technical Field
The present invention relates to a semiconductor device.
2. Background Art
In recent years, there has been a measure of reducing the height of contact in logic circuit section, aiming at increasing operation speed of semiconductor devices. A technique of this sort is known by the one described in Japanese Laid-Open Patent Publication No. 2007-201101 (Patent Document 1). According to Patent Document 1, upper electrodes of capacitance elements are connected by upper capacitor interconnects which are formed at the same level of height with interconnects in a logic circuit section, and thereby, the aspect ratio of the contact (logic contact) in the logic circuit section may be reduced while ensuring a sufficient level of film thickness of capacitance elements, needing neither processes solely required for forming interconnects, called plate line, for connecting the upper electrodes, nor dedicated equipment.
Also various proposals have been made on techniques for similarly reducing the height of contact in the logic circuit section [see Japanese Laid-Open Patent Publication Nos. 2004-342787 (Patent Document 2) and 2008-251763 (Patent Document 3), for example].
Patent Document 2 describes that a first-layer interconnect is formed in the middle position of the capacitance elements, in order to reduce the height of contact, and thereby the height of contact in the logic circuit section may be reduced similarly as described in Patent Document 1.
Patent Document 3 describes that the height of contact in the logic circuit section may be reduced, by providing an assist interconnect in the same layer with pads to be connected to the lower electrodes of the capacitance elements, and in the peripheral circuit region.